List of Intel's Microprocessors

List of Intel microprocessors

The 4-bit processors

First single-chip microprocessor

*. Introduced November 15, 1971

*. Clock rate 740 kHz

*. 0.07 MIPS

*. Bus Width 8 bits (multiplexed address/data due to limited pins)

*. PMOS

*. Number of Transistors 2,300 at 10 um

*. Addressable Memory 640 bytes

*. Program Memory 4 KB (4 KB)

*. One of the earliest Commercial Microprocessors (cf. Four Phase Systems AL1, F14 CADC)

*. Originally designed to be used in Busicom calculator
MCS-4 Family:

*. 4004- CPU

*. 4001- ROM & 4 Bit Port

*. 4002- RAM & 4 Bit Port

*. 4003-10 Bit Shift Register

*. 4008-Memory+I/O Interface

*. 4009-Memory+I/O Interface

Intel 4040

MCS-40 Family:

*. 4040-CPU

*. 4101-1024-bit (256 - 4) Static RAM with separate I/O

*. 4201-4 MHz Clock Generator

*. 4207-General Purpose Byte I/O Port

*. 4209-General Purpose Byte I/O Port

*. 4211-General Purpose Byte I/O Port

*. 4265-Programmable General Purpose I/O Device

*. 4269-Programmable Keyboard Display Device

*. 4289-Standard Memory Interface for MCS-4/40

*. 4308-8192-bit (1024 - 8) ROM w/ 4-bitI/O Ports

*. 4316-16384-bit (2048 - 8) Static ROM

*. 4702-2048-bit (256 - 8) EPROM

*. 4801-5.185 MHz Clock Generator Crystal for 4004/4201A or 4040/4201A

The 8-bit processors

8008

*. Introduced April 1, 1972

*. Clock rate 500 kHz (8008-1: 800 kHz)

*. 0.05 MIPS

*. Bus Width 8 bits (multiplexed address/data due to limited pins)

*. Enhancement load PMOS logic

*. Number of Transistors 3,500 at 10 um

*. Addressable memory 16 KB

*. Typical in early 8 bit microcomputers, dumb terminals, general calculators, bottling machines

*. Developed in tandem with 4004

*. Originally intended for use in the Data point 2200 microcomputer

*. Key volume deployment in Texas Instruments 742 microcomputer in>3,000 Ford dealerships

8080

*. Introduced April 1, 1974

*. Clock rate 2 MHz (very rare 8080B: 3 MHz)

*. 0.64 MIPS

*. Bus Width 8 bits data, 16 bits address

*. Enhancement load NMOS logic

*. Number of Transistors 6,000

*. Assembly language downwards compatible with 8008.

*. Addressable memory 64 KB

*. Up to 10X the performance of the 8008

*. Used in the Altair 8800, Traffic light controller, cruise missile

*. Required six support chips versus 20 for the 8008

8085

*. Introduced March 1976

*. Clock rate 3 MHz

*. 0.37 MIPS

*. Bus Width 8 bits data, 16 bits address

*. Depletion load NMOS logic

*. Number of Transistors 6,500 at 3m

*. Binary compatible downwards with the 8080.

*. Used in Toledo scales. Also was used as a computer peripheral controller - modems, hard disks, printers, etc...

*. CMOS 80C85 in Mars Sojourner, Radio Shack Model 100 portable.

*. High level of integration, operating for the first time on a single 5 volt power supply, from 12 volts previously. Also featured serial I/O, 3 maskable interrupts, 1 Non-maskable interrupt, 1 externally expandable interrupt w/[8259], status,  DMA.

MCS-85 Family:

*. 8155-RAM+ 3 I/O Ports + Timer "Active Low CS"

*. 8185-SRAM

*. 8202-Dynamic RAM Controller

*. 8203-Dynamic RAM Controller

*. 8205-1 Of 8 Binary Decoder

*. 8206-Error Detection & Correction Unit

*. 8207-DRAM Controller

*. 8210-TTL To MOS Shifter & High Voltage Clock Driver

*. 8216-4 Bit Parallel Bidirectional Bus Driver

*. 8219-Bus Controller

*. 8222-Dynamic RAM Refresh Controller

*. 8226-4 Bit Parallel Bidirectional Bus Driver

*. 8232-Floating Point Processor

*. 8237-DMA Controller

*. 8251-Communication Controller

*. 8253-Programmable Interval Timer

*. 8254-Programmable Interval Timer

*. 8255-Programmable Peripheral Interface

*. 8256-Multifunction Support Controller

*. 8257-DMA Controller

*. 8259-Programmable Interrupt Controller

*. 8271-Programmable Floppy Disk Controller

*. 8272-Single/Double Density Floppy Disk Controller

*. 8273-Programmable HDLC/SDLC Protocol Controller

*. 8274-Multi-Protocol Serial Controller

*. 8275-CRT Controller

*. 8276-Small System CRT Controller

*. 8279-KeyBoard/Display Controller

*. 8283-8-bit Inverting Latch with Output Buffer

*. 8291-GPIB Talker/Listener

*. 8292-GPIB Controller

*. 8293-GPIB Transceiver

*. 8294-Data Encryption/Decryption Unit+1 O/P Port

*. 8295-Dot Matrix Printer Controller

*. 8296-GPIB Transceiver

*. 8297-GPIB Transceiver

*. 8355-16,384-bit (2048 - 8) ROM with I/O

*. 8755-EPROM+2 I/O Ports

Microcontrollers

They are ICs with CPU, RAM, ROM (or PROM or EPROM), I/O Ports, Timers & Interrupts

Intel 8048

*. Single accumulator Harvard architecture
MCS-48 family:

*. 8020-Single-Component 8-Bit Microcontroller

*. 8021-Single-Component 8-Bit Microcontroller

*. 8022-Single-Component 8-Bit Microcontroller With On Chip A/D Converter

*. 8035-Single-Component 8-Bit Microcontroller

*. 8039-Single-Component 8-Bit Microcontroller

*. 8040-Single-Component 8-Bit Microcontroller

*. 8041-Universal Peripheral Interface 8-Bit Slave Microcontroller

*. 8641-Universal Peripheral Interface 8-Bit Slave Microcontroller

*. 8741-Universal Peripheral Interface 8-Bit Slave Microcontroller

*. 8042-Universal Peripheral Interface 8-Bit Slave Microcontroller

*. 8742-Universal Peripheral Interface 8-Bit Slave Microcontroller

*. 8243-Input/Output Expander

*. 8048-Single-Component 8-Bit Microcontroller

*. 8048-Single-Component 8-Bit Microcontroller

*. 8748-Single-Component 8-Bit Microcontroller

*. 8048-Single-Component 8-Bit Microcontroller

*. 8049-Single-Component 8-Bit Microcontroller

*. 8749-Single-Component 8-Bit Microcontroller

*. 8050-Single-Component 8-Bit Microcontroller

Intel 8051

*. Single accumulator Harvard architecture
MCS-51 Family:

*. 8031-8-Bit Control-Oriented Microcontroller

*. 8032-8-Bit Control-Oriented Microcontroller

*. 8044-High Performance 8-Bit Microcontroller

*. 8344-High Performance 8-Bit Microcontroller

*. 8744-High Performance 8-Bit Microcontroller

*. 8051-8-Bit Control-Oriented Microcontroller

*. 8052-8-Bit Control-Oriented Microcontroller

*. 8054-8-Bit Control-Oriented Microcontroller

*. 8058-8-Bit Control-Oriented Microcontroller

*. 8351-8-Bit Control-Oriented Microcontroller

*. 8352-8-Bit Control-Oriented Microcontroller

*. 8354-8-Bit Control-Oriented Microcontroller

*. 8358-8-Bit Control-Oriented Microcontroller

*. 8751-8-Bit Control-Oriented Microcontroller

*. 8752-8-Bit Control-Oriented Microcontroller

*. 8754-8-Bit Control-Oriented Microcontroller

*. 8758-8-Bit Control-Oriented Microcontroller

*. 80151-8-Bit Control-Oriented Microcontroller

*. 83151-8-Bit Control-Oriented Microcontroller

*. 87151-8-Bit Control-Oriented Microcontroller

*. 80152-8-Bit Control-Oriented Microcontroller

*. 83152-8-Bit Control-Oriented Microcontroller

*. 80251-8-Bit Control-Oriented Microcontroller

*. 87251-8-Bit Control-Oriented Microcontroller

MCS-96 Family

*. 8094-16-Bit Microcontroller (48-Pin ROMLess Without A/D)

*. 8095-16-Bit Microcontroller (48-Pin ROMLess With A/D)

*. 8096-16-Bit Microcontroller (68-Pin ROMLess Without A/D)

*. 8097-16-Bit Microcontroller (68-Pin ROMLess With A/D)

*. 8394-16-Bit Microcontroller (48-Pin With ROM Without A/D)

*. 8395-16-Bit Microcontroller (48-Pin With ROM With A/D)

*. 8396-16-Bit Microcontroller (68-Pin With ROM Without A/D)]

*. 8397-16-Bit Microcontroller (68-Pin With ROM With A/D)

*. 8794-16-Bit Microcontroller (48-Pin With EROM Without A/D)

*. 8795-16-Bit Microcontroller (48-Pin With EROM With A/D)

*. 8796-16-Bit Microcontroller (68-Pin With EROM Without A/D)

*. 8797-16-Bit Microcontroller (68-Pin With EROM With A/D)

*. 8098-16-Bit Microcontroller

*. 8398-16-Bit Microcontroller

*. 8798-16-Bit Microcontroller

*. 80196-16-Bit Microcontroller

*. 83196-16-Bit Microcontroller

*. 87196-16-Bit Microcontroller

*. 80296-16-Bit Microcontroller

The bit-slice processor

3000 Family

*. 3001-Microcontrol Unit

*. 3002-2-bit Arithmetic Logic Unit slice

*. 3003-Look-ahead Carry Generator

*. 3205-High-performance 1 Of 8 Binary Decoder

*. 3207-Quad Bipolar-to-MOS Level Shifter and Driver

*. 3208-Hex Sense Amp and Latch for MOS Memories

*. 3210-TTL-to-MOS Level Shifter and High Voltage Clock Driver

*. 3211-ECL-to-MOS Level Shifter and High Voltage Clock Driver

*. 3212-Multimode Latch Buffer

*. 3214-Interrupt Control Unit

*. 3216-Parallel, Inverting Bi-Directional Bus Driver

*. 3222-Refresh Controller for 4K NMOS DRAMs

*. 3226-Parallel, Inverting Bi-Directional Bus Driver

*. 3232-Address Multiplexer and Refresh Counter for 4K DRAMs

*. 3242-Address Multiplexer and Refresh Counter for 16K DRAMs

*. 3245-Quad Bipolar TTL-to-MOS Level Shifter and Driver for 4K

*. 3246-Quad Bipolar ECL-to-MOS Level Shifter and Driver for 4K

*. 3404-High-performance 6-bit Latch

*. 3408-Hex Sense Amp and Latch for MOS Memories

The 16-bit processors: origin of x86

8086

*. Introduced June 8, 1978

*. Clock rates:

*. 4.77 MHz with 0.33 MIPS

*. 8 MHz with 0.66 MIPS

*. 10 MHz with 0.75 MIPS

*. The memory is divided into odd and even banks; it accesses both banks concurrently to read 16 bits of data in one clock cycle

*. Bus Width 16 bits data, 20 bits address

*. Number of Transistors 29,000 at 3m

*. Addressable memory 1 megabyte

*. Up to 10X the performance of 8080 (usually lower)

*. Used in portable computing, and in the IBM PS/2 Model 25 and Model 30. Also used in the AT&T PC6300 / Olivetti M24, a popular IBM PC-compatible (predating the IBM PS/2 line.)

*. Used segment registers to access more than 64 KB of data at once, which many programmers complained made their work excessively difficult.

8088

*. Introduced June 1, 1979

*. Clock rates:

*. 4.77 MHz with 0.33 MIPS

*. 8 MHz with 0.75 MIPS

*. Internal architecture 16 bits

*. External bus Width 8 bits data, 20 bits address

*. Number of Transistors 29,000 at 3um

*. Addressable memory 1 megabyte

*. Identical to 8086 except for its 8 bit external bus (hence an 8 instead of a 6at the end)

*. Used in IBM PCs and PC clones

MCS-86 Family

*. 8086-CPU

*. 8088 -CPU

*. 8087-Math Coprocessor

*. 8089 -Programmable DMA Coprocessor

*. 8208-Dynamic RAM Controller

*. 8282 8-Bit-Latch

*. 8283 8-Bit-Latch

*. 8284 Clock Generator & Driver

*. 8286 Octal Bus Transceiver

*. 8287 Octal Bus Transceiver

*. 8288 Bus Controller

*. 8289 Bus Arbiter

*. 80130 iRMX 86 Operating System Processors

*. 80186 -CPU

*. 80188 -CPU

*. 80286 -CPU

*. 80287 -Math-Coprocessor

*. 82050 Communication Controller

*. 82062 Winchester Disk Controller

*. 82064 Floppy Disk Controller

*. 82091 Advanced Integrated Peripheral

*. 82188 Bus Controller

*. 82288 Bus Controller

*. 82389 Message Passing Coprocessor

*. 82503 Dual Serial Transceiver

*. 82510-Communication Controller

*. 82530 Serial Communication Controller

*. 82577 -PCI LAN Controller

*. 82586 IEEE 802.3 EtherNET LAN CoProcessor

*. 82596 LAN-CoProcessor

*. 82720 Graphics Display Controller

*. 82730 Text Coprocessor

*. 80386 -CPU

*. 80387 -Math-CoProcessor

80186

*. Introduced 1982

*. Clock rates

*. 6 MHz with > 1 MIPS

*. Number of Transistors 29,000 at 2um

*. Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor (These were at fixed addresses which differed from the IBM PC, making it impossible to build a 100% PC-compatible computer around the 80186.)

*. Added a few opcodes and exceptions to the 8086 design; otherwise identical instruction set to 8086 and 8088.

*. Used mostly in embedded applications - controllers, point-of-sale systems, terminals, and the like

*. Used in several non-PC-Compatible MS-DOS computers including RM Nimbus, Tandy 2000, and CP/M 86 Televideo PM16 server

*. Later renamed the iAPX 186

80188

*. A version of the 80186 with an 8-bit external data bus

*. Later renamed the iAPX 188

80286

*. Introduced February 1, 1982

*. Clock rates:

*. 6 MHz with 0.9 MIPS

*. 8 MHz, 10 MHz with 1.5 MIPS

*. 12.5 MHz with 2.66 MIPS

*. 16 MHz, 20 MHz and 25 MHz available.

*. Bus Width: 16 bit data, 24 bit address.

*. Included memory protection hardware to support multitasking operating systems with per-process address space

*. Number of Transistors 134,000 at 1.5um

*. Addressable memory 16 MB (16 MB)

*. Added protected-mode features to 8086 with essentially the same instruction set

*. 3-6X the performance of the 8086

*. Widely used in IBM-PC AT and AT clones contemporary to it

 

32-bit processors: the non-x86 microprocessors

iAPX 432

*. Introduced January 1, 1981 as Intel's first 32-bit microprocessor

*. Multi-chip CPU; Intel's first 32-bit microprocessor

*. Object/capability architecture

*. Microcoded operating system primitives

*. One terabyte virtual address space

*. Hardware support for fault tolerance

*. Two-chip General Data Processor (GDP), consists of 43201 and 43202

*. 43203 Interface Processor (IP) interfaces to I/O subsystem

*. 43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems

*. 43205 Memory Control Unit (MCU)

*. Architecture and execution unit internal data base paths 32 bit

*. Clock rates:

*. 5 MHz

*. 7 MHz

*. 8 MHz

i960 aka 80960

*. Introduced April 5, 1988

*. RISC -like 32-bit architecture

*. Predominantly used in embedded systems

*. Evolved from the capability processor developed for the BiiN joint venture with Siemens

*. Many variants identified by two-letter suffixes.

80386SX (chronological entry)

*. Introduced June 16, 1988

80376 (chronological entry)

*. Introduced January 16, 1989

i860 aka 80860

*. Introduced February 27, 1989

*. RISC 32/64-bit architecture, with floating point pipeline characteristics very visible to programmer

*. Used in the Intel iPSC/860 Hypercube parallel supercomputer

*. mid-life kicker in the i870 processor (primarily a speed bump, some refinement/extension of instruction set)

*. Used in the Intel Delta massively parallel supercomputer prototype, emplaced at California Institute of Technology

*. Used in the Intel Paragon massively parallel supercomputer, emplaced at Sandia National Laboratory

XScale

*. Introduced August 23, 2000

*. 32-bit RISC microprocessor based on the ARM architecture

*. Many variants, such as the PXA2xx applications processors, IOP3xx I/O processors and IXP2xxx and IXP4xx network processors.

 

32-bit processors: the 80386 range

80386DX

*. Introduced October 17, 1985

*. Clock rates:

*. 16 MHz with 5 to 6 MIPS

*. 20 MHz with 6 to 7 MIPS, introduced February 16, 1987

*. 25 MHz with 8.5 MIPS, introduced April 4, 1988

*. 33 MHz with 11.4 MIPS (9.4 SPECint92 on Compaq/i 16K L2), introduced April 10, 1989

*. Bus Width 32 bit data, 32 bit address

*. Number of Transistors 275,000 at 1um

*. Addressable memory 4 GB (4 GB)

*. Virtual memory 64 TB (64 TB)

*. First x86 chip to handle 32-bit data sets

*. Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required at the time by Xenix and Unix. This memory capability spurred the development and availability of OS/2 and is a fundamental requirement for modern operating systems like Linux, Vista, and Mac OS.

*. Used in Desktop computing

80960 (i960) (chronological entry)

*. Introduced April 5, 1988

80386SX

*. Introduced June 16, 1988

*. Clock rates:

*. 16 MHz with 2.5 MIPS

*. 20 MHz with 2.5 MIPS, introduced January 25, 1989

*. 25 MHz with 2.7 MIPS, introduced January 25, 1989

*. 33 MHz with 2.9 MIPS, introduced October 26, 1992

*. Internal architecture 32 bits

*. External data bus width 16 bits

*. External address bus width 24 bits

*. Number of Transistors 275,000 at 1um

*. Addressable memory 16 MB

*. Virtual memory 32 GB

*. Narrower buses enable low-cost 32-bit processing

*. Used in entry-level desktop and portable computing

*. No Math Co-Processor

*. No commercial Software used for protected mode or virtual storage for many years

80376

*. Introduced January 16, 1989; Discontinued June 15, 2001

*. Variant of 386SX intended for embedded systems

*. No "real mode", starts up directly in "protected mode"

*. Replaced by much more successful 80386EX from 1994

80860 (i860) (chronological entry)

*. Introduced February 27, 1989

80486DX (chronological entry)

*. Introduced April 10, 1989

80386SL

*. Introduced October 15, 1990

*. Clock rates:

*. 20 MHz with 4.21 MIPS

*. 25 MHz with 5.3 MIPS, introduced September 30, 1991

*. Internal architecture 32 bits

*. External bus width 16 bits

*. Number of Transistors 855,000 at 1um

*. Addressable memory 4 GB

*. Virtual memory 1 TB

*. First chip specifically made for portable computers because of low power consumption of chip

*. Highly integrated, includes cache, bus, and memory controllers

80486SX/DX2/SL, Pentium, 80486DX4 (chronological entries)

*. Introduced 1991-1994

80386EX

*. Introduced August 1994

*. Variant of 80386SX intended for embedded systems

*. Static core, i.e. may run as slowly (and thus, power efficiently) as desired, down to full halt

*. On-chip peripherals:

*. Clock and power mgmt

*. Timers/counters

*. Watchdog timer

*. Serial I/O units (sync and async) and parallel I/O

*. DMA

*. RAM refresh

*. JTAG test logic

*. Significantly more successful than the 80376

*. Used aboard several orbiting satellites and microsatellites

*. Used in NASA's Flight Linux project

 

32-bit processors: the 80486 range

80486DX

*. Introduced April 10, 1989

*. Clock rates:

*. 25 MHz with 20 MIPS (16.8 SPECint92, 7.40 SPECfp92)

*. 33 MHz with 27 MIPS (22.4 SPECint92 on Micronics M4P 128 KB L2), introduced May 7, 1990

*. 50 MHz with 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256 KB L2), introduced June 24, 1991

*. Bus Width 32 bits

*. Number of Transistors 1.2 million at 1um; the 50 MHz was at 0.8um

*. Addressable memory 4 GB

*. Virtual memory 1 TB

*. Level 1 cache of 8 KB on chip

*. Math coprocessor on chip

*. 50X performance of the 8088

*. Used in Desktop computing and servers

*. Family 4 model 3

80386SL (chronological entry)

*. Introduced October 15, 1990

80486SX

*. Introduced April 22, 1991

*. Clock rates:

*. 16 MHz with 13 MIPS

*. 20 MHz with 16.5 MIPS, introduced September 16, 1991

*. 25 MHz with 20 MIPS (12 SPECint92), introduced September 16, 1991

*. 33 MHz with 27 MIPS (15.86 SPECint92), introduced September 21, 1992

*. Bus Width 32 bits

*. Number of Transistors 1.185 million at 1um and 900,000 at 0.8um

*. Addressable memory 4 GB

*. Virtual memory 1 TB

*. Identical in design to 486DX but without math coprocessor. The first version was an 80486DX with disabled mathcore in the chip and different pin configuration. If the user needed math co capabilities, he must add 487SX which was actually an 486DX with different pin configuration to prevent the user from installing a 486DX instead of 487SX, so with this configuration 486SX+487SX you had 2 identical CPU's with only 1 turned on

*. Used in low-cost entry to 486 CPU desktop computing, as well as extensively used in low cost mobile computing.

*. Upgradable with the Intel Over Drive processor

*. Family 4 model 2

80486DX2

*. Introduced March 3, 1992

*. Clock rates:

*. 40 MHz

*. 50 MHz

*. 66 MHz

*. 100 MHz (This was only made a short time due to high failure rates.)

80486SL

*. Introduced November 9, 1992

*. Clock rates:

*. 20 MHz with 15.4MIPS

*. 25 MHz with 19 MIPS

*. 33 MHz with 25 MIPS

*. Bus Width 32 bits

*. Number of Transistors 1.4 million at 0.8um

*. Addressable memory 4 GB

*. Virtual memory 1 TB

*. Used in notebook computers

*. Family 4 model 3

Pentium (chronological entry)

*. Introduced March 22, 1993

80486DX4

*. Introduced March 7, 1994

*. Clock rates:

*. 75 MHz with 53 MIPS (41.3 SPECint92, 20.1 SPECfp92 on Micronics M4P 256 KB L2)

*. 100 MHz with 70.7 MIPS (54.59 SPECint92, 26.91 SPECfp92 on Micronics M4P 256 KB L2)

*. Number of Transistors 1.6 million at 0.6um

*. Bus width 32 bits

*. Addressable memory 4 GB

*. Virtual memory 64 TB

*. Pin count 168 PGA Package, 208 sq ftP Package

*. Used in high performance entry-level desktops and value notebooks

*. Family 4 model 8

 

32-bit processors: P5 microarchitecture

Original Pentium

*. Bus width 64 bits

*. System bus clock rate 60 or 66 MHz

*. Address bus 32 bits

*. Addressable Memory 4 GB

*. Virtual Memory 64 TB

*. Superscalar architecture

*. Runs on 5 volts

*. Used in desktops

*. 8 KB of instruction cache

*. 8 KB of data cache

P5 - 0.8um process technology

*. Introduced March 22, 1993

*. Number of transistors 3.1 million

*. Socket 4 273 pin PGA processor package

*. Package dimensions 2.16" - 2.16"

*. Family 5 model 1

Variants

*. 60 MHz with 100 MIPS (70.4 SPECint92, 55.1 SPECfp92 on Xpress 256 KB L2)

*. 66 MHz with 112 MIPS (77.9 SPECint92, 63.6 SPECfp92 on Xpress 256 KB L2)

P54 - 0.6um process technology

*. Socket 5 296/320 pin PGA package

*. Number of transistors 3.2 million

Variants

*. 75 MHz Introduced October 10, 1994

*. 90, 100 MHz Introduced March 7, 1994

P54CQS - 0.35um process technology

*. Socket 5 296/320 pin PGA package

*. Number of transistors 3.2 million

Variants

*. 120 MHz Introduced March 27, 1995

P54CS - 0.35um process technology

*. Number of transistors 3.3 million

*. 90 mm² die size

*. Family 5 model 2

Variants

*. Socket 5 296/320 pin PGA package

*. 133 MHz Introduced June 12, 1995

*. 150, 166 MHz Introduced January 4, 1996

*. Socket 7 296/321 pin PGA package

*. 200 MHz Introduced June 10, 1996

Pentium with MMX Technology

P55C - 0.35um process technology

*. Introduced January 8, 1997

*. Intel MMX (instruction set) support

*. Socket 7 296/321 pin PGA (pin grid array) package

*. 16 KB L1 instruction cache

*. 16 KB L1 data cache

*. Number of transistors 4.5 million

*. System bus clock rate 66 MHz

*. Basic P55C is family 5 model 4, mobile are family 5 model 7 and 8

Variants

*. 166, 200 MHz Introduced January 8, 1997

*. 233 MHz Introduced June 2, 1997

*. 133 MHz (Mobile)

*. 166, 266 MHz (Mobile) Introduced January 12, 1998

*. 200, 233 MHz (Mobile) Introduced September 8, 1997

*. 300 MHz (Mobile) Introduced January 7, 1999

 

32-bit processors:   P6 / Pentium M microarchitecture

Pentium Pro

*. Introduced November 1, 1995

*. Precursor to Pentium II and III

*. Primarily used in server systems

*. Socket 8 processor package (387 pins) (Dual SPGA)

*. Number of transistors 5.5 million

*. Family 6 model 1

0.6 um process technology

*. 16 KB L1 cache

*. 256 KB integrated L2 cache

*. 60 MHz system bus clock rate

Variants

*. 150 MHz

0.35um process technology or 0.35um CPU with 0.6um L2 cache

*. Number of transistors 5.5 million

*. 512 KB or 256 KB integrated L2 cache

*. 60 or 66 MHz system bus clock rate

Variants

*. 166 MHz (66 MHz bus clock rate, 512 KB 0.35um cache) Introduced November 1, 1995

*. 180 MHz (60 MHz bus clock rate, 256 KB 0.6um cache) Introduced November 1, 1995

*. 200 MHz (66 MHz bus clock rate, 256 KB 0.6um cache) Introduced November 1, 1995

*. 200 MHz (66 MHz bus clock rate, 512 KB 0.35um cache) Introduced November 1, 1995

*. 200 MHz (66 MHz bus clock rate, 1 MB 0.35um cache) Introduced August 18, 1997

Pentium II

*. Introduced May 7, 1997

*. Pentium Pro with MMX and improved 16-bit performance

*. 242-pin Slot 1 (SEC) processor package

*. Slot 1

*. Number of transistors 7.5 million

*. 32 KB L1 cache

*. 512 KB - bandwidth external L2 cache

*. The only Pentium II that did not have the L2 cache at ½ bandwidth of the core was the Pentium II 450 PE.

Klamath - 0.35um process technology (233, 266, 300 MHz)

*. 66 MHz system bus clock rate

*. Family 6 model 3

Variants

*. 233, 266, 300 MHz Introduced May 7, 1997

Deschutes - 0.25um process technology (333, 350, 400, 450 MHz)

*. Introduced January 26, 1998

*. 66 MHz system bus clock rate (333 MHz variant), 100 MHz system bus clock rate for all models after

*. Family 6 model 5

Variants

*. 333 MHz Introduced January 26, 1998

*. 350, 400 MHz Introduced April 15, 1998

*. 450 MHz Introduced August 24, 1998

*. 233, 266 MHz (Mobile) Introduced April2, 1998

*. 333 MHz Pentium II Overdrive processor for Socket 8 Introduced August 10, 1998; Engineering Sample Photo

*. 300 MHz (Mobile) Introduced September 9, 1998

*. 333 MHz (Mobile)

Celeron (Pentium II-based)

Covington - 0.25um process technology

*. Introduced April 15, 1998

*. 242-pin Slot 1 SEPP (Single Edge Processor Package)

*. Number of transistors 7.5 million

*. 66 MHz system bus clock rate

*. Slot 1

*. 32 KB L1 cache

*. No L2 cache

Variants

*. 266 MHz Introduced April 15, 1998

*. 300 MHz Introduced June 9, 1998

Mendocino - 0.25um process technology

*. Introduced August 24, 1998

*. 242-pin Slot 1 SEPP (Single Edge Processor Package), Socket 370 PPGA package

*. Number of transistors 19 million

*. 66 MHz system bus clock rate

*. Slot 1, Socket 370

*. 32 KB L1 cache

*. 128 KB integrated cache

*. Family 6 model 6

Variants

*. 300, 333 MHz Introduced August 24, 1998

*. 366, 400 MHz Introduced January 4, 1999

*. 433 MHz Introduced March 22, 1999

*. 466 MHz

*. 500 MHz Introduced August 2, 1999

*. 533 MHz Introduced January 4, 2000

*. 266 MHz (Mobile)

*. 300 MHz (Mobile)

*. 333 MHz (Mobile) Introduced April 5, 1999

*. 366 MHz (Mobile)

*. 400 MHz (Mobile)

*. 433 MHz (Mobile)

*. 450 MHz (Mobile) Introduced February 14, 2000

*. 466 MHz (Mobile)

*. 500 MHz (Mobile) Introduced February 14, 2000

Pentium II Xeon (chronological entry)

*. Introduced June 29, 1998

Pentium III

Katmai - 0.25um process technology

*. Introduced February 26, 1999

*. Improved PII, i.e. P6-based core, now including Streaming SIMD Extensions (SSE)

*. Number of transistors 9.5 million

*. 512 KB ½ bandwidth L2 External cache

*. 242-pin Slot 1 SECC2 (Single Edge Contact cartridge 2) processor package

*. System Bus clock rate 100 MHz, 133 MHz (B-models)

*. Slot 1

*. Family 6 model 7

Variants

*. 450, 500 MHz Introduced February 26, 1999

*. 550 MHz Introduced May 17, 1999

*. 600 MHz Introduced August 2, 1999

*. 533, 600 MHz Introduced (133 MHz bus clock rate) September 27, 1999

Coppermine - 0.18um process technology

*. Introduced October 25, 1999

*. Number of transistors 28.1 million

*. 256 KB Advanced Transfer L2 Cache (Integrated)

*. 242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin FC-PGA (Flip-chip pin grid array) package

*. System Bus clock rate 100 MHz (E-models), 133 MHz (EB models)

*. Slot 1, Socket 370

*. Family 6 model 8

Variants

*. 500 MHz (100 MHz bus clock rate)

*. 533 MHz

*. 550 MHz (100 MHz bus clock rate)

*. 600 MHz

*. 600 MHz (100 MHz bus clock rate)

*. 650 MHz (100 MHz bus clock rate) Introduced October 25, 1999

*. 667 MHz Introduced October 25, 1999

*. 700 MHz (100 MHz bus clock rate) Introduced October 25, 1999

*. 733 MHz Introduced October 25, 1999

*. 750, 800 MHz (100 MHz bus clock rate) Introduced December 20, 1999

*. 850 MHz (100 MHz bus clock rate) Introduced March 20, 2000

*. 866 MHz Introduced March 20, 2000

*. 933 MHz Introduced May 24, 2000

*. 1000 MHz Introduced March 8, 2000 (Not widely available at time of release)

*. 1100 MHz

*. 1133 MHz (first version recalled, later re-released)

*. 400, 450, 500 MHz (Mobile) Introduced October 25, 1999

*. 600, 650 MHz (Mobile) Introduced January 18, 2000

*. 700 MHz (Mobile) Introduced April 24, 2000

*. 750 MHz (Mobile) Introduced June 19, 2000

*. 800, 850 MHz (Mobile) Introduced September 25, 2000

*. 900, 1000 MHz (Mobile) Introduced March 19, 2001

Tualatin - 0.13um process technology

*. Introduced July 2001

*. Number of transistors 28.1 million

*. 32 KB L1 cache

*. 256 KB or 512 KB Advanced Transfer L2 cache (Integrated)

*. 370-pin FC-PGA2 (Flip-chip pin grid array) package

*. 133 MHz system bus clock rate

*. Socket 370

*. Family 6 model 11

Variants

*. 1133 MHz (256 KB L2)

*. 1133 MHz (512 KB L2)

*. 1200 MHz

*. 1266 MHz (512 KB L2)

*. 1333 MHz

*. 1400 MHz (512 KB L2)

Pentium II and III Xeon

PII Xeon

Variants

*. 400 MHz Introduced June 29, 1998

*. 450 MHz (512 KB L2 Cache) Introduced October 6, 1998

*. 450 MHz (1 MB and 2 MB L2 Cache) Introduced January 5, 1999

PIII Xeon

*. Introduced October 25, 1999

*. Number of transistors: 9.5 million at 0.25um or 28 million at 0.18 um

*. L2 cache is 256 KB, 1 MB, or 2 MB Advanced Transfer Cache (Integrated)

*. Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330

*. System Bus clock rate 133 MHz (256 KB L2 cache) or 100 MHz (1 - 2 MB L2cache)

*. System Bus Width 64 bit

*. Addressable memory 64 GB

*. Used in two-way servers and workstations (256 KB L2) or 4- and 8-way servers (1 - 2 MB L2)

*. Family 6 model 10

Variants

*. 500 MHz (0.25um process) Introduced March 17, 1999

*. 550 MHz (0.25um process) Introduced August 23, 1999

*. 600 MHz (0.18um process, 256 KB L2cache) Introduced October 25, 1999

*. 667 MHz (0.18um process, 256 KB L2 cache) Introduced October 25, 1999

*. 733 MHz (0.18um process, 256 KB L2 cache) Introduced October 25, 1999

*. 800 MHz (0.18um process, 256 KB L2 cache) Introduced January 12, 2000

*. 866 MHz (0.18um process, 256 KB L2 cache) Introduced April 10, 2000

*. 933 MHz (0.18um process, 256 KB L2 cache)

*. 1000 MHz (0.18um process, 256 KB L2cache) Introduced August 22, 2000

*. 700 MHz (0.18um process, 1 - 2 MB L2 cache) Introduced May 22, 2000

Celeron (Pentium III Coppermine-based)

Coppermine-128, 0.18um process technology

*. Introduced March, 2000

*. Streaming SIMD Extensions (SSE)

*. Socket 370, FC-PGA processor package

*. Number of transistors 28.1 million

*. 66 MHz system bus clock rate, 100 MHz system bus clock rate from January 3, 2001

*. 32 KB L1 cache

*. 128 KB Advanced Transfer L2 cache

*. Family 6 model 8

Variants

*. 533 MHz

*. 566 MHz

*. 600 MHz

*. 633, 667, 700 MHz Introduced June 26, 2000

*. 733, 766 MHz Introduced November 13, 2000

*. 800 MHz Introduced January 3, 2001

*. 850 MHz Introduced April 9, 2001

*. 900 MHz Introduced July 2, 2001

*. 950, 1000, 1100 MHz Introduced August 31, 2001

*. 550 MHz (Mobile)

*. 600, 650 MHz (Mobile) Introduced June19, 2000

*. 700 MHz (Mobile) Introduced September 25, 2000

*. 750 MHz (Mobile) Introduced March 19, 2001

*. 800 MHz (Mobile)

*. 850 MHz (Mobile) Introduced July 2, 2001

*. 600 MHz (LV Mobile)

*. 500 MHz (ULV Mobile) Introduced January 30, 2001

*. 600 MHz (ULV Mobile)

XScale (chronological entry)

*. Introduced August 23, 2000

Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon, Itanium 2 (chronological entries)

*. Introduced April 2000 - July 2002

Celeron (Pentium III Tualatin-based)

Tualatin Celeron - 0.13um process technology

*. 32 KB L1 cache

*. 256 KB Advanced Transfer L2 cache

*. 100 MHz system bus clock rate

*. Socket 370

*. Family 6 model 11

Variants

*. 1.0 GHz

*. 1.1 GHz

*. 1.2 GHz

*. 1.3 GHz

*. 1.4 GHz

Pentium M

Banias 0.13 um process technology

*. Introduced March 2003

*. 64 KB L1 cache

*. 1 MB L2 cache (integrated)

*. Based on Pentium III core, with SSE2 SIMD instructions and deeper pipeline

*. Number of transistors 77 million

*. Micro-FCPGA , Micro-FCBGA processor package

*. Heart of the Intel mobile Centrino system

*. 400 MHz Netburst-style system bus

*. Family 6 model 9

Variants

*. 900 MHz (Ultra low voltage)

*. 1.0 GHz (Ultra low voltage)

*. 1.1 GHz (Low voltage)

*. 1.2 GHz (Low voltage)

*. 1.3 GHz

*. 1.4 GHz

*. 1.5 GHz

*. 1.6 GHz

*. 1.7 GHz

Dothan 0.09 m (90 nm) process technology

*. Introduced May 2004

*. 2 MB L2 cache

*. 140 million transistors

*. Revised data prefetch unit

*. 400 MHz Netburst-style system bus

*. 21W TDP

*. Family 6 model 13

Variants

*. 1.00 GHz (Pentium M 723) (Ultra low voltage, 5W TDP)

*. 1.10 GHz (Pentium M 733) (Ultra low voltage, 5W TDP)

*. 1.20 GHz (Pentium M 753) (Ultra low voltage, 5W TDP)

*. 1.30 GHz (Pentium M 718) (Low voltage, 10W TDP)

*. 1.40 GHz (Pentium M 738) (Low voltage, 10W TDP)

*. 1.50 GHz (Pentium M 758) (Low voltage, 10W TDP)

*. 1.60 GHz (Pentium M 778) (Low voltage, 10W TDP)

*. 1.40 GHz (Pentium M 710)

*. 1.50 GHz (Pentium M 715)

*. 1.60 GHz (Pentium M 725)

*. 1.70 GHz (Pentium M 735)

*. 1.80 GHz (Pentium M 745)

*. 2.00 GHz (Pentium M 755)

*. 2.10 GHz (Pentium M 765)

Dothan 533 0.09 um (90 nm) process technology

*. Introduced Q1 2005

*. Same as Dothan except with a 533 MHz NetBurst-style system bus and 27W TDP

Variants

*. 1.60 GHz (Pentium M 730)

*. 1.73 GHz (Pentium M 740)

*. 1.86 GHz (Pentium M 750)

*. 2.00 GHz (Pentium M 760)

*. 2.13 GHz (Pentium M 770)

*. 2.26 GHz (Pentium M 780)

Stealey 0.09 um (90 nm) process technology

*. Introduced Q2 2007

*. 512 KB L2, 3W TDP

Variants

*. 600 MHz (A100)

*. 800 MHz (A110)

Celeron M

Banias -512 0.13 um process technology

*. Introduced March 2003

*. 64 KB L1 cache

*. 512 KB L2 cache (integrated)

*. SSE2 SIMD instructions

*. No Speed Step technology, is not part of the ' Centrino ' package

*. Family 6 model 9

Variants

*. 310 - 1.20 GHz

*. 320 - 1.30 GHz

*. 330 - 1.40 GHz

*. 340 - 1.50 GHz

Dothan -1024 90 nm process technology

*. 64 KB L1 cache

*. 1 MB L2 cache (integrated)

*. SSE2 SIMD instructions

*. No Speed Step technology, is not part of the ' Centrino ' package

Variants

*. 350 - 1.30 GHz

*. 350J - 1.30 GHz, with Execute Disable bit

*. 360 - 1.40 GHz

*. 360J - 1.40 GHz, with Execute Disable bit

*. 370 - 1.50 GHz, with Execute Disable bit

*. Family 6, Model 13, Stepping 8

*. 380 - 1.60 GHz, with Execute Disable bit

*. 390 - 1.70 GHz, with Execute Disable bit

Yonah -1024 65 nm process technology

*. 64 KB L1 cache

*. 1 MB L2 cache (integrated)

*. SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit

*. No Speed Step technology, is not part of the ' Centrino ' package

Variants

*. 410 - 1.46 GHz

*. 420 - 1.60 GHz,

*. 423 - 1.06 GHz (ultra-low voltage)

*. 430 - 1.73 GHz

*. 440 - 1.86 GHz

*. 443 - 1.20 GHz (ultra-low voltage)

*. 450 - 2.00 GHz

Intel Core

Yonah 0.065 um (65 nm) process technology

*. Introduced January 2006

*. 533/667 MHz front side bus

*. 2 MB (Shared on Duo) L2 cache

*. SSE3 SIMD instructions

*. 31W TDP (T versions)

*. Family 6, Model 14

Variants:

*. Intel Core Duo T2700 2.33 GHz

*. Intel Core Duo T2600 2.16 GHz

*. Intel Core Duo T2500 2 GHz

*. Intel Core Duo T2450 2 GHz

*. Intel Core Duo T2400 1.83 GHz

*. Intel Core Duo T2300 1.66 GHz

*. Intel Core Duo T2050 1.6 GHz

*. Intel Core Duo T2300e 1.66 GHz

*. Intel Core Duo T2080 1.73 GHz

*. Intel Core Duo L2500 1.83 GHz (Low voltage, 15W TDP)

*. Intel Core Duo L2400 1.66 GHz (Low voltage, 15W TDP)

*. Intel Core Duo L2300 1.5 GHz (Low voltage, 15W TDP)

*. Intel Core Duo U2500 1.2 GHz (Ultra low voltage, 9W TDP)

*. Intel Core Solo T1350 1.86 GHz (533 FSB)

*. Intel Core Solo T1300 1.66 GHz

*. Intel Core Solo T1200 1.5 GHz

Dual-Core Xeon LV

Sossaman 0.065 um (65 nm) process technology

*. Introduced March 2006

*. Based on Yonah core, with SSE3 SIMD instructions

*. 667 MHz frontside bus

*. 2 MB Shared L2 cache

Variants

*. 2.0 GHz

32-bit processors: NetBurst microarchitecture

Pentium 4

0.18 um process technology (1.40 and 1.50 GHz)

*. Introduced November 20, 2000

*. L2 cache was 256 KB Advanced Transfer Cache (Integrated)

*. Processor Package Style was PGA423, PGA478

*. System Bus clock rate 400 MHz

*. SSE2 SIMD Extensions

*. Number of Transistors 42 million

*. Used in desktops and entry-level workstations

0.18 um process technology (1.7 GHz)

*. Introduced April 23, 2001

0.18 um process technology (1.6 and 1.8 GHz)

*. Introduced July 2, 2001

*. Core Voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in Battery Optimized Mode

*. Power <1 watt in Battery Optimized Mode

*. Used in full-size and then light mobile PCs

0.18 um process technology Willamette (1.9 and 2.0 GHz)

*. Introduced August 27, 2001

*. Family 15 model 1

Pentium 4 (2 GHz, 2.20 GHz)

*. Introduced January 7, 2002

Pentium 4 (2.4 GHz)

*. Introduced April 2, 2002

0.13 um process technology Northwood A (1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6, 2.8(OEM), 3.0 (OEM) GHz)

*. Improved branch prediction and other microcodes tweaks

*. 512 KB integrated L2 cache

*. Number of transistors 55 million

*. 400 MHz system bus.

*. Family 15 model 2

0.13 um process technology Northwood B (2.26, 2.4, 2.53, 2.66, 2.8, 3.06 GHz)

*. 533 MHz system bus. (3.06 includes Intel's hyper threading technology).

0.13 um process technology Northwood C (2.4, 2.6, 2.8, 3.0, 3.2, 3.4 GHz)

*. 800 MHz system bus (all versions include Hyper Threading)

*. 6500 to 10000 MIPS

Itanium (chronological entry)

*. Introduced 2001

Xeon

*. Official designation now Xeon, i.e. not "Pentium 4 Xeon"

Xeon 1.4, 1.5, 1.7 GHz

*. Introduced May 21, 2001

*. L2 cache was 256 KB Advanced Transfer Cache (Integrated)

*. Processor Package Style was Organic Land Grid Array 603 (OLGA 603)

*. System Bus clock rate 400 MHz

*. SSE2 SIMD Extensions

*. Used in high-performance and mid-range dual processor enabled workstations

Xeon 2.0 GHz and up to 3.6 GHz

*. Introduced September 25, 2001

Itanium 2 (chronological entry)

*. Introduced July 2002

Mobile Pentium 4-M

0.13 um process technology

*. 55 million transistors

*. Cache L2 512 KB

*. BUS a 400 MHz

*. Supports up to 1 GB of DDR 266 MHz Memory

*. Supports ACPI 2.0 and APM 1.2 System Power Management

*. 1.3 V - 1.2 V (Speed Step)

*. Power: 1.2 GHz 20.8 W, 1.6 GHz 30 W, 2.6 GHz 35 W

*. Sleep Power 5 W (1.2 V)

*. Deeper Sleep Power = 2.9 W (1.0 V)

Variants

*. 1.40 GHz - 23 April 2002

*. 1.50 GHz - 23 April 2002

*. 1.60 GHz - 4 March 2002

*. 1.70 GHz - 4 March 2002

*. 1.80 GHz - 23 April 2002

*. 1.90 GHz - 24 June 2002

*. 2.00 GHz - 24 June 2002

*. 2.20 GHz - 16 September 2002

*. 2.40 GHz - 14 January 2003

*. 2.50 GHz - 16 April 2003

*. 2.60 GHz - 11 June 2003

Pentium 4 EE

*. Introduced September 2003

*. EE = "Extreme Edition"

*. Built from the Xeon's "Gallatin" core, but with 2 MB cache-

Pentium 4E

*. Introduced February 2004

*. Built on 0.09 um (90 nm) process technology Prescott (2.4A, 2.8, 2.8A, 3.0, 3.2, 3.4, 3.6, 3.8) 1 MB L2 cache

*. 533 MHz system bus (2.4A and 2.8A only)

*. Number of Transistors 125 million on 1 MB Models

*. Number of Transistors 169 million on 2 MB Models

*. 800 MHz system bus (all other models)

*. Hyper-Threading support is only available on CPUs using the 800 MHz system bus.

*. The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even greater bandwidth.

*. 7500 to 11000 MIPS

*. LGA 775 versions are in the 5xx series (32-bit) and 5x1 series (with Intel 64)

*. The 6xx series has 2 MB L2 cache and Intel 64

Pentium 4F

*. Introduced Spring 2004

*. Same core as 4E, "Prescott"

*. 3.2-3.6 GHz

*. Starting with the D0 stepping of this processor, Intel 64 64-bit extensions has also been incorporated

64-bit processors: IA-64

*. New instruction set, not at all related to x86.

*. Before the feature was eliminated (Montecito, July 2006) IA-64 processors supported 32-bit x86 in hardware, but slowly

Itanium

*. Code name Merced

*. Family 0x07

*. Released May 29, 2001

*. 733 MHz and 800 MHz

*. 2MB cache

*. All recalled and replaced by Itanium-II

Itanium 2

*. Family 0x1F

*. Released July 2002

*. 900 MHz - 1.6 GHz

*. McKinley 900 MHz 1.5MB cache, Model 0x0

*. McKinley 1 GHz, 3MB cache, Model 0x0

*. Deerfield 1 GHz, 1.5MB cache, Model 0x1

*. Madison 1.3 GHz, 3MB cache, Model 0x1

*. Madison 1.4 GHz, 4MB cache, Model 0x1

*. Madison 1.5 GHz, 6MB cache, Model 0x1

*. Madison 1.67 GHz, 9MB cache, Model 0x1

*. Hondo 1.4 GHz, 4MB cache, dual core MCM, Model 0x1

64-bit processors: Intel 64 - NetBurst microarchitecture

*. Intel Extended Memory 64 Technology

*. Mostly compatible with AMD's AMD64 architecture

*. Introduced Spring 2004, with the Pentium 4F (D0 and later P4 stepping)

Pentium 4F

*. Prescott-2M built on 0.09 um (90 nm) process technology

*. 2.8-3.8 GHz (model numbers 6x0)

*. Introduced February 20, 2005

*. Same features as Prescott with the addition of:-

*. 2 MB cache

*. Intel 64bit

*. Enhanced Intel Speed Step Technology (EIST)

*. Cedar Mill built on 0.065 um (65 nm) process technology

*. 3.0-3.6 (model numbers 6x1)

*. Introduced January 16, 2006

*. Die shrink of Prescott-2M

*. Same features as Prescott-2M

*. Family 15 Model 4

Pentium D

*. Dual-core microprocessor

*. No Hyper-Threading

*. 800(4-200) MHz front side bus

*. LGA 775 (Socket T)

Smithfield - 90 nm process technology (2.66-3.2 GHz)

*. Introduced May 26, 2005

*. 2.66-3.2 GHz (model numbers 805-840)

*. Number of Transistors 230 million

*. 1 MB - 2 (non-shared, 2 MB total) L2 cache

*. Cache coherency between cores requires communication over the FSB

*. Performance increase of 60% over similarly clocked Prescott

*. 2.66 GHz (533 MHz FSB) Pentium D 805 introduced December 2005

*. Contains 2x Prescott dies in one package

*. Family 15 Model 4

Presler - 65 nm process technology (2.8-3.6 GHz)

*. Introduced January 16, 2006

*. 2.8-3.6 GHz (model numbers 915-960)

*. Number of Transistors 376 million

*. 2 MB - 2 (non-shared, 4 MB total) L2 cache

*. Contains 2x Cedar Mill dies in one package

Pentium Extreme Edition

Smithfield - 90 nm process technology (3.2 GHz)

*. Dual-core microprocessor

*. Enabled Hyper-Threading

*. 800(4-200) MHz front side bus

Variants

*. Pentium 840 EE - 3.20 GHz (2 - 1 MB L2)

Presler - 65 nm process technology (3.46, 3.73)

*. 2 MB - 2 (non-shared, 4 MB total) L2 cache

Variants

*. Pentium 955 EE - 3.46 GHz, 1066 MHz front side bus

*. Pentium 965 EE - 3.73 GHz, 1066 MHz front side bus

Xeon

Nocona

*. Introduced 2004

Irwindale

*. Introduced 2004

Cranford

*. Introduced April 2005

*. MP version of Nocona

Potomac

*. Introduced April 2005

*. Cranford with 8 MB of L3 cache

Paxville DP (2.8 GHz)

*. Introduced October 10, 2005

*. Dual-core version of Irwindale, with 4 MB of L2 Cache (2 MB per core)

*. 2.8 GHz

*. 800 MT/s front side bus

Paxville MP - 90 nm process (2.67 - 3.0 GHz)

*. Introduced November 1, 2005

*. Dual-Core Xeon 7000 series

*. MP-capable version of Paxville DP

*. 2 MB of L2 Cache (1 MB per core) or 4MB of L2 (2 MB per core)

*. 667 MT/s FSB or 800 MT/s FSB

Dempsey - 65 nm process (2.67 - 3.73 GHz)

*. Introduced May 23, 2006

*. Dual-Core Xeon 5000 series

*. MP version of Presler

*. 667 MT/s or 1066 MT/s FSB

*. 4 MB of L2 Cache (2 MB per core)

*. LGA 771 (Socket J).

Tulsa - 65 nm process (2.5 - 3.4 GHz)

*. Introduced August 29, 2006

*. Dual-Core Xeon 7100-series

*. Improved version of Paxville MP

*. 667 MT/s or 800 MT/s FSB

64-bit processors: Intel 64 - Core microarchitecture

Xeon

Woodcrest - 65 nm process technology

*. Server and Workstation CPU (SMP support for dual CPU system)

*. Introduced June 26, 2006

*. Dual-Core

*. Intel VT-x, multiple OS support

*. EIST (Enhanced Intel Speed Step Technology) in 5140, 5148LV, 5150, 5160

*. Execute Disable Bit

*. TXT, enhanced security hardware extensions

*. SSSE3 SIMD instructions

*. iAMT2 (Intel Active Management Technology), remotely manage computers

Variants

*. Xeon 5160 - 3.00 GHz (4 MB L2, 1333 MHz FSB, 80 W)

*. Xeon 5150 - 2.66 GHz (4 MB L2, 1333 MHz FSB, 65 W)

*. Xeon 5140 - 2.33 GHz (4 MB L2, 1333 MHz FSB, 65 W)

*. Xeon 5130 - 2.00 GHz (4 MB L2, 1333 MHz FSB, 65 W)

*. Xeon 5120 - 1.86 GHz (4 MB L2, 1066 MHz FSB, 65 W)

*. Xeon 5110 - 1.60 GHz (4 MB L2, 1066 MHz FSB, 65 W)

*. Xeon 5148LV - 2.33 GHz (4 MB L2, 1333 MHz FSB, 40 W) - Low Voltage Edition

Clovertown - 65 nm process technology

*. Server and Workstation CPU (SMP support for dual CPU system)

*. Introduced December 13, 2006

*. Quad Core

*. Intel VT-x , multiple OS support

*. EIST (Enhanced Intel Speed Step Technology) in E5365, L5335

*. Execute Disable Bit

*. TXT, enhanced security hardware extensions

*. SSSE3 SIMD instructions

*. iAMT2 (Intel Active Management Technology), remotely manage computers

Variants

*. Xeon X5355 - 2.66 GHz (2-4 MB L2, 1333 MHz FSB, 105 W)

*. Xeon E5345 - 2.33 GHz (2-4 MB L2, 1333 MHz FSB, 80 W)

*. Xeon E5335 - 2.00 GHz (2-4 MB L2, 1333 MHz FSB, 80 W)

*. Xeon E5320 - 1.86 GHz (2-4 MB L2, 1066 MHz FSB, 65 W)

*. Xeon E5310 - 1.60 GHz (2-4 MB L2, 1066 MHz FSB, 65 W)

*. Xeon L5320 - 1.86 GHz (2-4 MB L2, 1066 MHz FSB, 50 W) - Low Voltage Edition

Intel Core 2

Conroe - 65 nm process technology

*. Desktop CPU (SMP support restricted to 2 CPUs)

*. Two cores on one die

*. Introduced July 27, 2006

*. SSSE3 SIMD instructions

*. Number of Transistors: 291 Million

*. 64 KB of L1 cache per core (32+32 KB 8-way)

*. Intel VT-x, multiple OS support

*. TXT, enhanced security hardware extensions

*. Execute Disable Bit

*. EIST (Enhanced Intel Speed Step Technology)

*. iAMT2 (Intel Active Management Technology), remotely manage computers

*. LGA 775

Variants

*. Core 2 Duo E6850 - 3.00 GHz (4 MB L2, 1333 MHz FSB)

*. Core 2 Duo X6800 - 2.93 GHz (4 MB L2, 1066 MHz FSB)

*. Core 2 Duo E6750 - 2.67 GHz (4 MB L2, 1333 MHz FSB, 65W)

*. Core 2 Duo E6700 - 2.67 GHz (4 MB L2, 1066 MHz FSB)

*. Core 2 Duo E6600 - 2.40 GHz (4 MB L2, 1066 MHz FSB, 65W)

*. Core 2 Duo E6550 - 2.33 GHz (4 MB L2, 1333 MHz FSB)

*. Core 2 Duo E6420 - 2.13 GHz (4 MB L2, 1066 MHz FSB)

*. Core 2 Duo E6400 - 2.13 GHz (2 MB L2, 1066 MHz FSB)

*. Core 2 Duo E6320 - 1.86 GHz (4 MB L2, 1066 MHz FSB) Family 6, Model 15, Stepping 6

*. Core 2 Duo E6300 - 1.86 GHz (2 MB L2, 1066 MHz FSB)

Conroe XE - 65 nm process technology

*. Desktop Extreme Edition CPU (SMP support restricted to 2 CPUs)

*. Introduced July 27, 2006

*. same features as Conroe

*. LGA 775

Variants

*. Core 2 Extreme X6800 - 2.93 GHz (4 MB L2, 1066 MHz FSB)

Allendale - 65 nm process technology

*. Desktop CPU (SMP support restricted to 2 CPUs)

*. Two CPUs on one die

*. Introduced January 21, 2007

*. SSSE3 SIMD instructions

*. Number of Transistors 167 Million

*. TXT, enhanced security hardware extensions

*. Execute Disable Bit

*. EIST (Enhanced Intel Speed Step Technology)

*. iAMT2 (Intel Active Management Technology), remotely manage computers

*. LGA 775

Variants

*. Core 2 Duo E4700 - 2.60 GHz (2 MB L2, 800 MHz FSB)

*. Core 2 Duo E4600 - 2.40 GHz (2 MB L2, 800 MHz FSB)

*. Core 2 Duo E4500 - 2.20 GHz (2 MB L2, 800 MHz FSB)

*. Core 2 Duo E4400 - 2.00 GHz (2 MB L2, 800 MHz FSB)

*. Core 2 Duo E4300 - 1.80 GHz (2 MB L2, 800 MHz FSB) Family 6, Model 15, Stepping 2

Merom - 65 nm process technology

*. Mobile CPU (SMP support restricted to 2 CPUs)

*. Introduced July 27, 2006

*. Family 6, Model 15

*. Same features as Conroe

*. Socket M / Socket P

Variants

*. Core 2 Duo T7800 - 2.60 GHz (4 MB L2, 800 MHz FSB) (Santa Rosa platform)

*. Core 2 Duo T7700 - 2.40 GHz (4 MB L2, 800 MHz FSB)

*. Core 2 Duo T7600 - 2.33 GHz (4 MB L2, 667 MHz FSB)

*. Core 2 Duo T7500 - 2.20 GHz (4 MB L2, 800 MHz FSB)

*. Core 2 Duo T7400 - 2.16 GHz (4 MB L2, 667 MHz FSB)

*. Core 2 Duo T7300 - 2.00 GHz (4 MB L2, 800 MHz FSB)

*. Core 2 Duo T7250 - 2.00 GHz (2 MB L2, 800 MHz FSB)

*. Core 2 Duo T7200 - 2.00 GHz (4 MB L2, 667 MHz FSB)

*. Core 2 Duo T7100 - 1.80 GHz (2 MB L2, 800 MHz FSB)

*. Core 2 Duo T5600 - 1.83 GHz (2 MB L2, 667 MHz FSB) Family 6, Model 15, Stepping 6

*. Core 2 Duo T5550 - 1.83 GHz (2 MB L2, 667 MHz FSB, no VT)

*. Core 2 Duo T5500 - 1.66 GHz (2 MB L2, 667 MHz FSB, no VT)

*. Core 2 Duo T5470 - 1.60 GHz (2 MB L2, 800 MHz FSB, no VT)

*. Core 2 Duo T5450 - 1.66 GHz (2 MB L2, 667 MHz FSB, no VT)

*. Core 2 Duo T5300 - 1.73 GHz (2 MB L2, 533 MHz FSB, no VT)

*. Core 2 Duo T5270 - 1.40 GHz (2 MB L2, 800 MHz FSB, no VT)

*. Core 2 Duo T5250 - 1.50 GHz (2 MB L2, 667 MHz FSB, no VT)

*. Core 2 Duo T5200 - 1.60 GHz (2 MB L2, 533 MHz FSB, no VT)

*. Core 2 Duo L7500 - 1.60 GHz (4 MB L2, 800 MHz FSB) (Low Voltage)

*. Core 2 Duo L7400 - 1.50 GHz (4 MB L2, 667 MHz FSB) (Low Voltage)

*. Core 2 Duo L7300 - 1.40 GHz (4 MB L2, 800 MHz FSB) (Low Voltage)

*. Core 2 Duo L7200 - 1.33 GHz (4 MB L2, 667 MHz FSB) (Low Voltage)

*. Core 2 Duo U7700 - 1.33 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)

*. Core 2 Duo U7600 - 1.20 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)

*. Core 2 Duo U7500 - 1.06 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)

Kentsfield - 65 nm process technology

*. Two dual-core cpu dies in one package.

*. Desktop CPU Quad Core (SMP support restricted to 4 CPUs)

*. Introduced December 13, 2006

*. Same features as Conroe but with 4 CPU Cores

*. Number of Transistors 586 Million

*. LGA 775

*. Family 6, Model 15, Stepping 11

Variants

*. Core 2 Extreme QX6850 - 3 GHz (2-4 MB L2 Cache, 1333 MHz FSB)

*. Core 2 Extreme QX6800 - 2.93 GHz (2-4 MB L2 Cache, 1066 MHz FSB) (April 9, 2007)

*. Core 2 Extreme QX6700 - 2.66 GHz (2-4 MB L2 Cache, 1066 MHz FSB) (November 14, 2006)

*. Core 2 Quad Q6700 - 2.66 GHz (2-4 MB L2 Cache, 1066 MHz FSB) (July 22, 2007)

*. Core 2 Quad Q6600 - 2.40 GHz (2-4 MB L2 Cache, 1066 MHz FSB) (January7, 2007)

Wolfdale - 45 nm process technology

*. Die shrink of Conroe

*. Same features as Conroe with the addition of:-

*. 50% more cache, 6 MB as opposed to 4 MB

*. Intel Trusted Execution Technology

*. SSE4 SIMD instructions

*. Number of Transistors 410 Million

Variants

*. Core 2 Duo E8600 - 3.33 GHz (6 MB L2, 1333 MHz FSB)

*. Core 2 Duo E8500 - 3.16 GHz (6 MB L2, 1333 MHz FSB)

*. Core 2 Duo E8400 - 3.00 GHz (6 MB L2, 1333 MHz FSB)

*. Core 2 Duo E8300 - 2.83 GHz (6 MB L2, 1333 MHz FSB)

*. Core 2 Duo E8200 - 2.66 GHz (6 MB L2, 1333 MHz FSB)

*. Core 2 Duo E8190 - 2.66 GHz (6 MB L2, 1333 MHz FSB, no TXT, no VT)

Wolfdale-3M - 45 nm process technology

*. Intel Trusted Execution Technology

Variants

*. Core 2 Duo E7600 - 3.06 GHz (3 MB L2, 1066 MHz FSB)

*. Core 2 Duo E7500 - 2.93 GHz (3 MB L2, 1066 MHz FSB)

*. Core 2 Duo E7400 - 2.80 GHz (3 MB L2, 1066 MHz FSB)

*. Core 2 Duo E7300 - 2.66 GHz (3 MB L2, 1066 MHz FSB)

*. Core 2 Duo E7200 - 2.53 GHz (3 MB L2, 1066 MHz FSB)

Yorkfield - 45 nm process technology

*. Quad core CPU

*. Die shrink of Kentsfield

*. Contains 2x Wolfdale dual core dies in one package

*. Same features as Wolfdale

*. Number of Transistors 820 Million

Variants

*. Core 2 Extreme QX9770 - 3.20 GHz (2-6 MB L2, 1600 MHz FSB)

*. Core 2 Extreme QX9650 - 3.00 GHz (2-6 MB L2, 1333 MHz FSB)

*. Core 2 Quad Q9650 - 3 GHz (2-6 MB L2, 1333 MHz FSB)

*. Core 2 Quad Q9550 - 2.83 GHz (2-6 MB L2, 1333 MHz FSB, 95W TDP)

*. Core 2 Quad Q9550s - 2.83 GHz (2-6 MB L2, 1333 MHz FSB, 65W TDP)

*. Core 2 Quad Q9450 - 2.66 GHz (2-6 MB L2, 1333 MHz FSB, 95W TDP)

*. Core 2 Quad Q9505 - 2.83 GHz (2-3 MB L2, 1333 MHz FSB, 95W TDP)

*. Core 2 Quad Q9505s - 2.83 GHz (2-3 MB L2, 1333 MHz FSB, 65W TDP)

*. Core 2 Quad Q9500 - 2.83 GHz (2-3 MB L2, 1333 MHz FSB, 95W TDP, no TXT)

*. Core 2 Quad Q9400 - 2.66 GHz (2-3 MB L2, 1333 MHz FSB, 95W TDP)

*. Core 2 Quad Q9400s - 2.66 GHz (2-3 MB L2, 1333 MHz FSB, 65W TDP)

*. Core 2 Quad Q9300 - 2.50 GHz (2-3 MB L2, 1333 MHz FSB, 95W TDP)

*. Core 2 Quad Q8400 - 2.66 GHz (2-2 MB L2, 1333 MHz FSB, 95W TDP)

*. Core 2 Quad Q8400s - 2.66 GHz (2-2 MB L2, 1333 MHz FSB, 65W TDP)

*. Core 2 Quad Q8300 - 2.50 GHz (2-2 MB L2, 1333 MHz FSB, 95W TDP)

*. Core 2 Quad Q8300s - 2.50 GHz (2-2 MB L2, 1333 MHz FSB, 65W TDP)

*. Core 2 Quad Q8200 - 2.33 GHz (2-2 MB L2, 1333 MHz FSB, 95W TDP)

*. Core 2 Quad Q8200s - 2.33 GHz (2-2 MB L2, 1333 MHz FSB, 65W TDP)

*. Core 2 Quad Q7600 - 2.70 GHz (2-1 MB L2, 800 MHz FSB, no SSE4)

Intel Core2 Quad Mobile Processor Family - 45 nm process technology

*. Quad core CPU

Variants

*. Core 2 Quad Q9100 - 2.26 GHz (2-6 MB L2, 1066 MHz FSB, 45W TDP)

*. Core 2 Quad Q9000 - 2.00 GHz (2-3 MB L2, 1066 MHz FSB, 45W TDP)

Intel Pentium Dual Core

Allendale - 65 nm process technology

*. Desktop CPU (SMP support restricted to 2 CPUs)

*. Two cores on one die

*. Introduced January 21, 2007

*. SSSE3 SIMD instructions

*. Number of Transistors 167 Million

*. TXT, enhanced security hardware extensions

*. Execute Disable Bit

*. EIST (Enhanced Intel Speed Step Technology)

Variants

*. Intel Pentium E2220 - 2.40 GHz (1 MB L2, 800 MHz FSB)

*. Intel Pentium E2200 - 2.20 GHz (1 MB L2, 800 MHz FSB)

*. Intel Pentium E2180 - 2.00 GHz (1 MB L2, 800 MHz FSB)

*. Intel Pentium E2160 - 1.80 GHz (1 MB L2, 800 MHz FSB)

*. Intel Pentium E2140 - 1.60 GHz (1 MB L2, 800 MHz FSB)

Wolfdale-3M 45 nm process technology

*. Intel Pentium E6800 - 3.33 GHz (2 MB L2, 1066 MHz FSB)

*. Intel Pentium E6700 - 3.20 GHz (2 MB L2, 1066 MHz FSB)

*. Intel Pentium E6600 - 3.06 GHz (2 MB L2, 1066 MHz FSB)

*. Intel Pentium E6500 - 2.93 GHz (2 MB L2, 1066 MHz FSB)

*. Intel Pentium E6300 - 2.80 GHz (2 MB L2, 1066 MHz FSB)

*. Intel Pentium E5800 - 3.20 GHz (2 MB L2, 800 MHz FSB)

*. Intel Pentium E5700 - 3.00 GHz (2 MB L2, 800 MHz FSB)

*. Intel Pentium E5500 - 2.80 GHz (2 MB L2, 800 MHz FSB)

*. Intel Pentium E5400 - 2.70 GHz (2 MB L2, 800 MHz FSB)

*. Intel Pentium E5300 - 2.60 GHz (2 MB L2, 800 MHz FSB)

*. Intel Pentium E5200 - 2.50 GHz (2 MB L2, 800 MHz FSB)

*. Intel Pentium E2210 - 2.20 GHz (1 MB L2, 800 MHz FSB)

Celeron

Allendale - 65 nm process technology

Variants

*. Intel Celeron E1600 - 2.40 GHz (512 KB L2, 800 MHz FSB)

*. Intel Celeron E1500 - 2.20 GHz (512 KB L2, 800 MHz FSB)

*. Intel Celeron E1400 - 2.00 GHz (512 KB L2, 800 MHz FSB)

*. Intel Celeron E1300 - 1.80 GHz (512 KB L2, 800 MHz FSB) (Exist?)

*. Intel Celeron E1200 - 1.60 GHz (512 KB L2, 800 MHz FSB)

Wolfdale-3M - 45 nm process technology

Variants

*. Intel Celeron E3500 - 2.70 GHz (1 MB L2, 800 MHz FSB)

*. Intel Celeron E3400 - 2.60 GHz (1 MB L2, 800 MHz FSB)

*. Intel Celeron E3300 - 2.50 GHz (1 MB L2, 800 MHz FSB)

*. Intel Celeron E3200 - 2.40 GHz (1 MB L2, 800 MHz FSB)

Conroe-L - 65 nm process technology

Variants

*. Intel Celeron 450 - 2.20 GHz (512 KB L2, 800 MHz FSB)

*. Intel Celeron 440 - 2.00 GHz (512 KB L2, 800 MHz FSB)

*. Intel Celeron 430 - 1.80 GHz (512 KB L2, 800 MHz FSB)

*. Intel Celeron 420 - 1.60 GHz (512 KB L2, 800 MHz FSB)

*. Intel Celeron 220 - 1.20 GHz (512 KB L2, 533 MHz FSB)

Conroe-CL - 65 nm process technology

*. LGA 771 package

Variants

*. Intel Celeron 445 - 1.87 GHz (512 KB L2, 1066 MHz FSB)

Celeron M

Merom-L 65 nm process technology

*. 64 KB L1 cache

*. 1 MB L2 cache (integrated)

*. SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit, 64-bit

*. No Speed Step technology, is not part of the ' Centrino ' package

Variants

*. 520 - 1.60 GHz

*. 530 - 1.73 GHz

*. 540 - 1.86 GHz

*. 550 - 2.00 GHz

*. 560 - 2.13 GHz

64-bit processors: Intel 64 - Nehalem microarchitecture

Intel Pentium

Clarkdale - 32 nm process technology

*. 2 physical cores/2 threads

*. 3 MB L3 cache

*. Introduced January 2010

*. Socket 1156 LGA

*. 2-channels DDR3

*. Integrated HD GPU

Variants

*. G6950 - 2.8 GHz (No Hyper Threading)

*. G6960 - 2.933 GHz (No Hyper Threading)

Core i3 (1st Generation)

Clarkdale - 32 nm process technology

*. 2 physical cores/4 threads

*. 64 Kb L1 cache

*. 512 Kb L2 cache

*. 4 MB L3 cache

*. Introduced January, 2010

*. Socket 1156 LGA

*. 2-channels DDR3

*. Integrated HD GPU

Variants

*. 530 - 2.93 GHz Hyper-Threading

*. 540 - 3.06 GHz Hyper-Threading

*. 550 - 3.2 GHz Hyper-Threading

*. 560 - 3.33 GHz Hyper-Threading

Core i5 (1st Generation)

Lynnfield - 45 nm process technology

*. 4 physical cores

*. 32+32 Kb (per core) L1 cache

*. 256 Kb (per core) L2 cache

*. 8 MB common L3 cache

*. Introduced September 8, 2009

*. Family 6 Model E (Ext. Model 1E)

*. Socket 1156 LGA

*. 2-channels DDR3

Variants

*. 750S - 2.40 GHz/3.20 GHz Turbo Boost

*. 750 - 2.66 GHz/3.20 GHz Turbo Boost

*. 760 - 2.80 GHz/3.33 GHz Turbo Boost

Clarkdale - 32 nm process technology

*. 2 physical cores/4 threads

*. 64 Kb L1 cache

*. 512 Kb L2 cache

*. 4 MB L3 cache

*. Introduced January, 2010

*. Socket 1156 LGA

*. 2-channels DDR3

*. Integrated HD GPU

*. AES Support

Variants

*. 650/655K - 3.2 GHz Hyper-Threading Turbo Boost

*. 660/661 - 3.33 GHz Hyper-Threading Turbo Boost

*. 670 - 3.46 GHz Hyper-Threading Turbo Boost

*. 680 - 3.60 GHz Hyper-Threading Turbo Boost

Core i7 (1st Generation)

Bloomfield - 45 nm process technology

*. 4 physical cores

*. 256 KB L2 cache

*. 8 MB L3 cache

*. Front side bus replaced with Quick Path up to 6.4GT/s

*. Hyper-Threading is again included. This had previously been removed at the introduction of Core line

*. 781 million transistors

*. Intel Turbo Boost Technology

*. TDP 130W

*. Introduced November 17, 2008

*. Socket 1366 LGA

*. 3-channels DDR3

Variants

*. 975 (extreme edition) - 3.33 GHz/3.60 GHz Turbo Boost

*. 965 (extreme edition) - 3.20 GHz/3.46 GHz Turbo Boost

*. 960 - 3.20 GHz/3.46 GHz Turbo Boost

*. 950 - 3.06 GHz/3.33 GHz Turbo Boost

*. 940 - 2.93 GHz/3.20 GHz Turbo Boost

*. 930 - 2.80 GHz/3.06 GHz Turbo Boost

*. 920 - 2.66 GHz/2.93 GHz Turbo Boost

Lynnfield - 45 nm process technology

*. 4 physical cores

*. 256 KB L2 cache

*. 8 MB L3 cache

*. No Quick Path, instead compatible with slower DMI interface

*. Hyper-Threading is included

*. Introduced September 8, 2009

*. Socket 1156 LGA

*. 2-channels DDR3

Variants

*. 880 - 3.06 GHz/3.73 GHz Turbo Boost (TDP 95W)

*. 870/875K - 2.93 GHz/3.60 GHz Turbo Boost (TDP 95W)

*. 870S - 2.67 GHz/3.60 GHz Turbo Boost (TDP 82W)

*. 860 - 2.80 GHz/3.46 GHz Turbo Boost (TDP 95W)

*. 860S - 2.53 GHz/3.46 GHz Turbo Boost (TDP 82W)

TODO: Westmere

Gulftown - 32 nm process technology

*. 6 physical cores

*. 256 KB L2 cache

*. 12 MB L3 cache

*. Front side bus replaced with Quick Path up to 6.4GT/s

*. Hyper-Threading is included

*. Intel Turbo Boost Technology

*. Socket 1366 LGA

*. TDP 130W

*. Introduced 16 March 2010

Variants

*. 990X Extreme Edition - 3.46 GHz/3.73 GHz Turbo Boost

*. 980X Extreme Edition - 3.33 GHz/3.60 GHz Turbo Boost

*. 970 - 3.20 GHz/3.46 GHz Turbo Boost

Clarksfield - Intel Core i7 Mobile Processor Family - 45 nm process technology

*. 4 physical cores

*. Hyper-Threading is included

*. Intel Turbo Boost Technology

Variants

*. 940XM Extreme Edition - 2.13 GHz/3.33GHz Turbo Boost (8 MB L3, TDP 55W)

*. 920XM Extreme Edition - 2.00 GHz/3.20GHz Turbo Boost (8 MB L3, TDP 55W)

*. 840QM - 1.86 GHz/3.20 GHz Turbo Boost (8 MB L3, TDP 45W)

*. 820QM - 1.73 GHz/3.06 GHz Turbo Boost (8 MB L3, TDP 45W)

*. 740QM - 1.73 GHz/2.93 GHz Turbo Boost (6 MB L3, TDP 45W)

*. 720QM - 1.60 GHz/2.80 GHz Turbo Boost (6 MB L3, TDP 45W)

Xeon (Nehalem Microarchitecture)

Gainestown - 45 nm process technology

*. Same processor dies as Bloomfield

*. 256 KB L2 cache

*. 8 MB L3 cache, 4MB may be disabled

*. Quick Path up to 6.4GT/s

*. Hyper-Threading is included in some models

*. 781 million transistors

*. Introduced March 29, 2009

Variants

*. W5590, W5580, X5570, X5560, X5550, E5540, E5530, L5530, E5520, L5520, L5518 - 4 Cores, 8 MB L3 cache, HT

*. E5506, L5506, E5504 - 4 cores, 4 MB L3 cache, no HT

*. L5508, E5502, E5502 - 2 cores, 4 MB L3 cache, no HT

 

64-bit processors: Intel 64 - Sandy Bridge / Ivy Bridge microarchitecture

Celeron

Sandy Bridge - 32 nm process technology

*. 2 physical cores/2 threads (500 series),1 physical core/1 thread (model G440) or 1 physical core/2 threads (model G460)

*. 2 MB L3 cache (500 series), 1 MB (model G440) or 1.5 MB (model G460)

*. Introduced 3rd quarter, 2011

*. Socket 1155 LGA

*. 2-channels DDR3-1066

*. 400 series has max TDP of 35 W

*. 500-series variants ending in 'T' have a peak TDP of 35 W, others 65 W

*. Integrated GPU

*. All variants have peak GPU turbo frequencies of 1 GHz

*. Variants in the 400 series have GPUs running at a base frequency of 650 MHz

*. Variants in the 500 series ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz

*. All variants have 6 GPU execution units

Variants

*. G440 - 1.6 GHz

*. G460 - 1.8 GHz

*. G530T - 2.0 GHz

*. G530 - 2.4 GHz

*. G540 - 2.5 GHz

*. G550 - 2.6 GHz

Pentium

Sandy Bridge - 32 nm process technology

*. 2 physical cores/2 threads

*. 3 MB L3 cache

*. 624 million transistors

*. Introduced May, 2011

*. Socket 1155 LGA

*. 2-channels DDR3-1333 (800 series) or DDR3-1066 (600 series)

*. Variants ending in 'T' have a peak TDP of 35 W, others 65 W

*. Integrated GPU

*. All variants have peak GPU turbo frequencies of 1.1 GHz

*. Variants ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz

*. All variants have 6 GPU execution units

Variants

*. G620T - 2.2 GHz

*. G630T - 2.3 GHz

*. G620 - 2.6 GHz

*. G622 - 2.6 GHz

*. G630 - 2.7 GHz

*. G632 - 2.7 GHz

*. G840 - 2.8 GHz

*. G850 - 2.9 GHz

*. G860 - 3.0 GHz

*. G870 - 3.1 GHz

Core i3 (2nd and 3rd Generation)

Sandy Bridge - 32 nm process technology

*. 2 physical cores/4 threads

*. 32+32 Kb (per core) L1 cache

*. 256 Kb (per core) L2 cache

*. 3 MB L3 cache

*. 624 million transistors

*. Introduced January, 2011

*. Socket 1155 LGA

*. 2-channels DDR3-1333

*. Variants ending in 'T' have a peak TDP of 35 W, others 65 W

*. Integrated GPU

*. All variants have peak GPU turbo frequencies of 1.1 GHz

*. Variants ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz

*. Variants ending in '5' have Intel HD Graphics 3000 (12 execution units); others have Intel HD Graphics 2000 (6 execution units)

Variants

*. i3-2100T - 2.5 GHz

*. i3-2120T - 2.6 GHz

*. i3-2100 - 3.1 GHz

*. i3-2102 - 3.1 GHz

*. i3-2105 - 3.1 GHz

*. i3-2120 - 3.3 GHz

*. i3-2125 - 3.3 GHz

*. i3-2130 - 3.4 GHz

Ivy Bridge - 22 nm Tri-gate transistor process technology

*. 2 physical cores/4 threads

*. 32+32 Kb (per core) L1 cache

*. 256 Kb (per core) L2 cache

*. 3 MB L3 cache

*. Introduced September, 2012 (?)

*. Socket 1155 LGA

*. 2-channels DDR3-1600

*. Integrated GPU Intel HD Graphics 2500

*. TDP 55 W

Variants

*. i3-3220 - 3.3 GHz

Core i5 (2nd and 3rd Generation)

Sandy Bridge - 32 nm process technology

*. 4 physical cores/4 threads (except for i5-2390T which has 2 physical cores/4 threads)

*. 32+32 Kb (per core) L1 cache

*. 256 Kb (per core) L2 cache

*. 6 MB L3 cache (except for i5-2390T which has 3 MB)

*. 995 million transistors

*. Introduced January, 2011

*. Socket 1155 LGA

*. 2-channels DDR3-1333

*. Variants ending in 'S' have a peak TDP of 65 W, others 95 W except where noted

*. Variants ending in 'K' have unlocked multipliers; others cannot be over clocked

*. Integrated GPU

*. i5-2500T has a peak GPU turbo frequency of 1.25 GHz, others 1.1 GHz

*. Variants ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz

*. Variants ending in '5' or 'K' have Intel HD Graphics 3000 (12 execution units),except i5-2550K which has no GPU; others have Intel HD Graphics 2000 (6 execution units)

*. Variants ending in 'P' and the i5-2550K have no GPU

Variants

*. i5-2390T - 2.7 GHz/3.5 GHz Turbo Boost (35 W max TDP)

*. i5-2500T - 2.3 GHz/3.3 GHz Turbo Boost (45 W max TDP)

*. i5-2400S - 2.5 GHz/3.3 GHz Turbo Boost

*. i5-2405S - 2.5 GHz/3.3 GHz Turbo Boost

*. i5-2500S - 2.7 GHz/3.7 GHz Turbo Boost

*. i5-2300 - 2.8 GHz/3.1 GHz Turbo Boost

*. i5-2310 - 2.9 GHz/3.2 GHz Turbo Boost

*. i5-2320 - 3.0 GHz/3.3 GHz Turbo Boost

*. i5-2380P - 3.1 GHz/3.4 GHz Turbo Boost

*. i5-2400 - 3.1 GHz/3.4 GHz Turbo Boost

*. i5-2450P - 3.2 GHz/3.5 GHz Turbo Boost

*. i5-2500 - 3.3 GHz/3.7 GHz Turbo Boost

*. i5-2500K - 3.3 GHz/3.7 GHz Turbo Boost

*. i5-2550K - 3.4 GHz/3.8 GHz Turbo Boost

Ivy Bridge - 22 nm Tri-gate transistor process technology

*. 4 physical cores/4 threads (except for i5-3470T which has 2 physical cores/4 threads)

*. 32+32 Kb (per core) L1 cache

*. 256 Kb (per core) L2 cache

*. 6 MB L3 cache (except for i5-3470T which has 3 MB)

*. Introduced April, 2012

*. Socket 1155 LGA

*. 2-channels DDR3-1600

*. Variants ending in 'S' have a peak TDP of 65 W, Variants ending in 'T' have a peak TDP of 35 or 45 W (see variants), others 77 W except where noted

*. Variants ending in 'K' have unlocked multipliers; others cannot be overclocked

*. Integrated GPU Intel HD Graphics 2500or Intel HD Graphics 4000 (i5-3475S and i5-3570K only)

Variants

*. i5-3470T - 2.9 GHz/3.6 GHz max Turbo Boost (35 W TDP)

*. i5-3570T - 2.3 GHz/3.3 GHz max Turbo Boost (45 W TDP)

*. i5-3450S - 2.8 GHz/3.5 GHz max Turbo Boost

*. i5-3470S - 2.9 GHz/3.6 GHz max Turbo Boost

*. i5-3475S - 2.9 GHz/3.6 GHz max Turbo Boost

*. i5-3550S - 3.0 GHz/3.7 GHz max Turbo Boost

*. i5-3570S - 3.1 GHz/3.8 GHz max Turbo Boost

*. i5-3450 - 3.1 GHz/3.5 GHz max Turbo Boost

*. i5-3470 - 3.2 GHz/3.6 GHz max Turbo Boost

*. i5-3550 - 3.3 GHz/3.7 GHz max Turbo Boost

*. i5-3570 - 3.4 GHz/3.8 GHz max Turbo Boost

*. i5-3570K - 3.4 GHz/3.8 GHz max Turbo Boost

Core i7 (2nd and 3rd Generation)

Sandy Bridge - 32 nm process technology

*. 4 physical cores/8 threads

*. 32+32 Kb (per core) L1 cache

*. 256 Kb (per core) L2 cache

*. 8 MB L3 cache

*. 995 million transistors

*. Introduced January, 2011

*. Socket 1155 LGA

*. 2-channels DDR3-1333

*. Variants ending in 'S' have a peak TDP of 65 W, others 95 W

*. Variants ending in 'K' have unlocked multipliers; others cannot be over clocked

*. Integrated GPU

*. All variants have base GPU frequencies of 850MHz and peak GPU turbo frequencies of 1.35 GHz

*. Variants ending in 'K' have Intel HD Graphics 3000 (12 execution units); others have Intel HD Graphics 2000 (6 execution units)

Variants

*. i7-2600S - 2.8 GHz/3.8 GHz Turbo Boost

*. i7-2600 - 3.4 GHz/3.8 GHz Turbo Boost

*. i7-2600K - 3.4 GHz/3.8 GHz Turbo Boost

*. i7-2700K - 3.5 GHz/3.9 GHz Turbo Boost

Sandy Bridge-E - 32 nm process technology

*. Up to 8 physical cores/16 threads depending on model number

*. 32+32 Kb (per core) L1 cache

*. 256 Kb (per core) L2 cache

*. Up to 20 MB L3 cache depending on model number

*. 2270 million transistors

*. Introduced November, 2011

*. Socket 2011 LGA

*. 4-channels DDR3-1600

*. All variants have a peak TDP of 130 W

*. No integrated GPU

Variants

*. i7-3820 - 3.6 GHz/3.8 GHz Turbo Boost, 4 cores, 10 MB L3 cache

*. i7-3930K - 3.2 GHz/3.8 GHz Turbo Boost, 6 cores, 12 MB L3 cache

*. i7-3960X - 3.3 GHz/3.9 GHz Turbo Boost, 6 cores, 15 MB L3 cache

Ivy Bridge - 22 nm Tri-gate transistor process technology

*. 4 physical cores/8 threads

*. 32+32 Kb (per core) L1 cache

*. 256 Kb (per core) L2 cache

*. 8 MB L3 cache

*. Introduced April, 2012

*. Socket 1155 LGA

*. 2-channels DDR3-1600

*. Variants ending in 'S' have a peak TDP of 65 W, variants ending in 'T' have a peak TDP of 45 W, others 77 W

*. Variants ending in 'K' have unlocked multipliers; others cannot be over clocked

*. Integrated GPU Intel HD Graphics 4000

Variants

*. i7-3770T - 2.5 GHz/3.7 GHz Turbo Boost

*. i7-3770S - 3.1 GHz/3.9 GHz Turbo Boost

*. i7-3770 - 3.4 GHz/3.9 GHz Turbo Boost

*. i7-3770K - 3.5 GHz/3.9 GHz Turbo Boost

64-bit processors: Intel 64 – Haswell microarchitecture Edit
Core i3 (4th Generation)
*. Haswell (Core i3 4th Generation) – 22nm process technology

64-bit processors: Intel 64 – Broadwell microarchitecture Edit
Core i3 (5th Generation)
Broadwell (Core i3 5th Generation) – 14nm process technology

Core i5 (5th Generation)
Broadwell (Core i5 5th Generation) – 14nm process technology
*. 4 physical cores/4 threads
*. 4 MB L3 cache
*. Introduced Q2'15
*. Socket 1150 LGA
*. 2-channel DDR3L-1333/1600
*. Integrated GPU
Variants
*. i5-5575R – 2.80 GHz/3.30 GHz Turbo Boost
*. i5-5675C – 3.10 GHz/3.60 GHz Turbo Boost
*. i5-5675R – 3.10 GHz/3.60 GHz Turbo Boost

Core i7 (5th Generation, Including Core-X Series)
Broadwell (Core i7 5th Generation) – 14nm process technology
*. 4 physical cores/8 threads
*. 6 MB L3 cache
*. Introduced Q2'15
*. Socket 1150 LGA
*. 2-channel DDR3L-1333/1600
*. Integrated GPU
Variants
*. i7-5775C – 3.30 GHz/3.70 GHz Turbo Boost
*. i7-5775R – 3.30 GHz/3.80 GHz Turbo Boost

Broadwell-E – 14nm process technology
*. 6–10 physical cores/12–20 threads
*. 15–25 MB L3 cache
*. Introduced Q2'16
*. Socket 2011-v3 LGA
*. 4-channel DDR4-2133/2400
*. No Integrated GPU
Variants (all marketed under "Intel Core X-series Processors")
*. i7-6800K – 3.40 GHz/3.60 GHz Turbo Boost/3.80 GHz Turbo Boost Max Technology 3.0 Frequency 15 MB L3 cache
*. i7-6850K – 3.60 GHz/3.80 GHz Turbo Boost/4.00 GHz Turbo Boost Max Technology 3.0 Frequency 15 MB L3 cache
*. i7-6900K – 3.20 GHz/3.70 GHz Turbo Boost/4.00 GHz Turbo Boost Max Technology 3.0 Frequency 20 MB L3 cache
*. i7-6950X – 3.00 GHz/3.50 GHz Turbo Boost/4.00 GHz Turbo Boost Max Technology 3.0 Frequency 25 MB L3 cache

Other Broadwell CPUs
Not listed (yet) are several Broadwell-based CPU models:
Server and workstation CPUs
*. single-CPU: Pentium D15nn, Xeon D-15nn, Xeon E3-12nn v4, Xeon E5-16nn v4
*. dual-CPU: Xeon E5-26nn v4
*. quad-CPU: Xeon E5-46nn v4, Xeon E7-48nn v4
*. octo-CPU: Xeon E7-88nn v4

Embedded CPUs
*. Core i7-57nnEQ, Core i7-58nnEQ

Mobile CPUs
*. Celeron 32nnU, Celeron 37nnU
*. Pentium 38nnU
*. Core M-5Ynn
*. Core i3-50nnU
*. Core i5-5nnnU
*. Core i7-55nnU, Core i7-56nnU, Core i7-57nnHQ, Core i7-59nnHQ

Note: this list does not say that all processors that match these patterns are Broadwell-based or fit into this scheme. The model numbers may have suffixes that are not shown here.

64-bit processors: Intel 64 – Skylake microarchitecture Edit
Core i3 (6th Generation)
Skylake (Core i3 6th Generation) – 14 nm process technology
*. 2 physical cores/4 threads
*. 3–4 MB L3 cache
*. Introduced Q3'15
*. Socket 1151 LGA
*. 2-channel DDR3L-1333/1600, DDR4-1866/2133
*. Integrated GPU Intel HD Graphics 530 (only i3-6098P have HD Graphics 510)
Variants
*. i3-6098P – 3.60 GHz
*. i3-6100T – 3.20 GHz
*. i3-6100 – 3.70 GHz
*. i3-6300T – 3.30 GHz
*. i3-6300 – 3.80 GHz
*. i3-6320 – 3.90 GHz

Core i5 (6th Generation)
Skylake (Core i5 6th Generation) – 14nm process technology
*. 4 physical cores/4 threads
*. 6 MB L3 cache
*. Introduced Q3'15
*. Socket 1151 LGA
*. 2-channel DDR3L-1333/1600, DDR4-1866/2133
*. Integrated GPU Intel HD Graphics 530
Variants
*. i5-6400T – 2.20 GHz/2.80 GHz Turbo Boost
*. i5-6400 – 2.70 GHz/3.30 GHz Turbo Boost
*. i5-6500T – 2.50 GHz/3.10 GHz Turbo Boost
*. i5-6500 – 3.20 GHz/3.60 GHz Turbo Boost
*. i5-6600T – 2.70 GHz/3.50 GHz Turbo Boost
*. i5-6600 – 3.30 GHz/3.90 GHz Turbo Boost
*. i5-6600K – 3.50 GHz/3.90 GHz Turbo Boost

Core i7 (6th Generation)
Skylake (Core i7 6th Generation) – 14nm process technology
*. 4 physical cores/8 threads
*. 8 MB L3 cache
*. Introduced Q3'15
*. Socket 1151 LGA
*. 2-channel DDR3L-1333/1600, DDR4-1866/2133
*. Integrated GPU Intel HD Graphics 530
Variants
*. i7-6700T – 2.80 GHz/3.60 GHz Turbo Boost
*. i7-6700 – 3.40 GHz/4.00 GHz Turbo Boost
*. i7-6700K – 4.00 GHz/4.20 GHz Turbo Boost

Other Skylake Processors
Many Skylake-based processors are not yet listed in this section: mobile i3/i5/i7 processors (U, H, and M suffixes), embedded i3/i5/i7 processors (E suffix), certain i7-67nn/i7-68nn/i7-69nn. Skylake-based "Core X-series" processors (certain i7-78nn and i9-79nn models) can be found under current models.

64-bit processors: Intel 64 – Kaby Lake microarchitecture Edit
Main article: Kaby Lake (CPU)
64-bit processors: Intel 64 – Coffee Lake microarchitecture Edit
Main article: Coffee Lake (CPU)
64-bit processors: Intel 64 – Cannon Lake microarchitecture Edit
Main article: Cannon Lake (CPU)
64-bit processors: Intel 64 – Ice Lake microarchitecture Edit
Main article: Ice Lake (microprocessor)
64-bit processors: Intel 64 – Comet Lake microarchitecture

Main article: Comet Lake (CPU)

Cheers!!!

Source: Wikipedia

Updated and Edited by AdeDanCompTech